A multi-phase DC-DC converter uses a supervisory multi-channel controller to regulate the power delivered by multiple phases or power channels of the converter to an output node feeding a load. As a non-limiting example, FIG. 1 diagrammatically illustrates a conventional dual-phase DC-DC converter, which contains two power channels 100 and 200, that drive an output node OUT with an output voltage Vo. The output voltage is regulated by a supervisory controller 500, which monitors output currents ISEN1 and ISEN2 sensed at current sensing ports coupled to phase nodes 125 and 225 of respective power switching stages 120 and 220 of the two channels, and uses this current information to precisely control the pulse widths of associated streams of pulse width modulation (PWM) waveforms applied by respective PWM generators 10 and 20 to drivers 110 and 210 that control switching times of switching devices (e.g., MOSFETs) of the output power switching stages 120 and 220. The PWM waveforms are sequenced and timed such that the interval between rising edges (or in some implementations, falling edges) thereof is constant, for the purpose of equalizing the currents delivered by the two power channels. (The sum of the current measurements may also be also used to precisely regulate the output resistance in a method commonly known as droop regulation or load-line regulation.)
More particularly, in the two-phase DC-DC converter architecture of FIG. 1, the first power switching stage 120 is shown as including an upper power semiconductor switch (e.g., MOSFET) 121, and a lower power semiconductor switch (e.g., MOSFET) 122 having the source-drain paths thereof coupled in series between an input voltage (Vin) supply terminal 123 and a reference voltage (ground) terminal 124. The control or gate input of the upper MOSFET switch 121 is coupled to a first output 111 of the first channel driver 110, while the control or gate input of lower MOSFET switch 122 is coupled to a second output 112 of the first channel driver. The common or phase node 125 between the upper and lower MOSFET switches 121 and 122 provides a voltage V1P, and is coupled by way of an output inductor (Lo) 126 to the output node OUT, to which a first phase/channel output voltage V1N from the first power channel is applied. An output current sense resistor 127 (having a resistor value Rs) is coupled between the phase node 125 and a current sense node 129 by way of which a measure ISEN1 of the output current of the first channel is derived for application to the controller 500. A capacitor (Cs) 128 is coupled between current sense node 129 and the output node OUT.
In a like manner, the second power switching stage 220 contains an upper power semiconductor switch (MOSFET) 221, and a lower power semiconductor switch (MOSFET) 222 having the source-drain paths thereof coupled in series between the input voltage (Vin) supply terminal 123 and the reference voltage (ground) terminal 124. The control or gate input of upper MOSFET switch 221 is coupled to a first output 211 of the second channel driver 210, while the control or gate input of lower MOSFET switch 222 is coupled to a second output 212 of the second channel driver. The common or phase node 225 between the upper and lower MOSFET switches 221 and 222, which provides a voltage V2P, is coupled by way of an output inductor (Lo) 226 to the output node OUT, to which a second phase/channel output voltage V2N from the second power channel is applied. An output current sense resistor 227 (having a resistor value Rs) is coupled between the phase node 225 and a current sense node 229 by way of which a measure ISEN2 of the output current of the second channel is derived for application to the controller 500. A capacitor (Cs) 228 is coupled between current sense node 229 and the output node OUT.
To control the operation of the first power channel 100, controller 500 includes a first difference amplifier 510, which has a first, non-inverting (+) input 511 coupled to the first channel's current sense node 129, so as to receive a measure of the first sensed current ISEN1, and a second, inverting input (−) 512 coupled to receive a voltage representative of the average IAVG of the first and second currents ISEN1 and ISEN2 as produced by an averaging circuit 515. Averaging circuit 515 includes a summing unit 516 coupled to the two current sensed nodes 129 and 229 from which the sensed currents ISEN1 and ISEN2 are supplied. The output of summing unit 516 is coupled to a divide-by-two divider 517, which outputs a voltage representative of the average current value IAVG of the two sense currents ISEN1 and ISEN2. The output 513 of difference amplifier 510 is used to provide a first correction voltage ICOR1 representative of the difference between the first channel's sensed current ISEN1 and the average IAVG of the two sensed currents.
For controlling the operation of the second power channel 200, controller 500 includes a second difference amplifier 520, which has a first, non-inverting (+) input 521 thereof coupled to the second channel's current sense node 229, so as to receive a measure of the second sensed current ISEN2, and a second, inverting input (−) 522 coupled to receive the voltage representative of the average output IAVG of averaging circuit 515. The output 523 of difference amplifier 520 is used to provide a second correction voltage ICOR2 representative of the difference between the second channel's sensed current ISEN2 and the average IAVG of the two sensed currents.
The first correction voltage ICOR1 is coupled to a first (−) input 541 of a subtraction unit 540, which has a second (+) input 542 coupled to receive an error voltage generated at the output 553 of an error amplifier 550. Error amplifier 550 generates an error voltage representative of the difference between a reference voltage Vref coupled to a first, non-inverting (+) input 551 thereof, and the output voltage Vo that is fed back from the output node OUT to a second, inverting (−) input 551 thereof, and couples this error voltage to second (+) inputs 542 and 562 of respective subtraction units 540 and 560. Subtraction unit 560 has a first (−) input coupled to receive the second correction voltage ICOR2 at the output 523 of difference amplifier 520. The output 543 of subtraction unit 540 serves as the control input for the PWM modulator 10 of the first power channel 100, while the output 563 of subtraction unit 560 serves as the control input for the PWM modulator 20 of the second power channel 200.
In operation, any difference between the output voltage Vo sensed at the output terminal OUT and the reference voltage Vref produces an error voltage at the output of error amplifier 550. This error voltage constitutes a principal control metric for adjusting the PWM waveforms produced by PWM modulators 10 and 20 of the respective power channels/phases 100 and 200. Since it monitors the currents ISEN1 and ISEN2 sensed at the outputs of the two power channels 100 and 200, controller 500 is able to determine any imbalance in these currents for the two channels, by comparing each channel's sensed current with the average value IAVG of the sensed currents for both phases. Any difference between a sensed current for a respective channel i and the average IAVG of the sensed currents for the two channels results in a correction voltage ICORi that is used to offset or modify the error voltage produced by error amplifier 550, and thereby the pulse widths of the PWM waveforms generated by the PWM generators 10 and 20, so as to equalize the currents delivered by the two power channels.
Now although the output current monitoring and imbalance correction mechanism employed in the converter architecture of FIG. 1 is intended to effectively equalize the currents delivered by the two power channels, it can do so provided that the circuitry layouts of the respective power channels of the converter are symmetric with respect to one another. Otherwise—namely, in the case of a non-symmetric circuit layout—the output voltage V1N for the first channel/phase will not equal the output voltage V2N for the second channel/phase, resulting in a current imbalance between the different channels, and preventing the controller from equalizing the currents in the two power channels.
This lack of symmetry in the power channel circuit layouts of a multi-phase DC-DC converter—which is not uncommon as the number of power channels increases, and can be expected to be the case where the converter employs an odd number of channels/phases—is due principally to the fact that the distances from the controller to the most remote power channels increase substantially as the number of phases/channels increases. This makes it very difficult for the designer to preserve signal integrity of the current-sense lines, due to the fact that these lines typically traverse long distances through a noisy environment from the output current monitoring nodes and the controller, and the fact that the signals transmitted on the current-sense lines are voltage signals proportional to current, and voltage signals are prone to corruption from capacitively-coupled noise.